About this app

Notes on MOS ICs & Technology (integrated circuit) for easy learning and quick learning. This App is actually a handbook, which covers all the topics of the subject. You can consider this App as a notes which professors guides with in a classroom.

You can very easily pass and succeed in your exams and interviews if you have this App in your mobile phone, and give an overview for a few days.

It covers 114 topics of MOS ICs & Technology in detail. These 114 topics are divided in 8 units
Some of topics Covered in this application are:

1. Moore's Law.
2. Comparison of available technologies
3. Basic MOS Transistors
4. Enhancement mode Transistor action:
5. NMOS Fabrication:
6. CMOS fabrication- P-WELL PROCESS
7. CMOS fabrication-N-WELL PROCESS:
8. CMOS fabrication-Twin-tub process
9. Bi-CMOS technology: - (Bipolar CMOS):
10. Production of e-beam masks
11. Introduction to MOS Transistor
12. Relationship between Vgs and Ids, for a fixed Vds
13. MOS equations (Basic DC equations):
14. Second Order Effects
15. CMOS INVETER CHARACTERISTICS
16. Inverter DC Characteristics
17. Graphical Derivation of Inverter DC Characteristics
18. Noise Margin
19. Static Load MOS inverters
20. Transmission gates
21. Tristate Inverter
22. Stick diagrams-Encodings for NMOS process
23. Encodings for CMOS process
24. Encoding for BJT and MOSFETs
25. NMOS and CMOS Design style
26. Design Rules - MOS ICs & Technology
27. Via
28. CMOS lambda based design rules
29. Orbit 2um CMOS process
30. Resistance estimation.
31. Sheet resistance of mos transistors
32. Capacitance estimation
33. Delay
34. Inverter delays
35. Formal estimation of delay
36. Driving large capacitive load
37. Optimum value of f
38. Super buffer
39. Bicmos drivers
40. Propagation delay
41. Other sources of capacitance
42. Choice of layers
43. Scaling of mos devices
44. Basic physical design an overview
45. Basic physical design an overview
46. Schematic and layout of basic gates-Inverter Gate
47. Schematic and layout of basic gates-NAND and NOR Gate
48. Transmission gate
49. CMOS standard cell design
50. Layout optimization for performance
51. General layout guidelines
52. BICMOS Logic
53. Pseudo nmos logic
54. Other variations of pseudo nmos- Multi drain logic and Ganged logic
55. Other variations of pseudo nmos- Dynamic cmos logic
56. Other variations of pseudo nmos- CLOCKED CMOS LOGIC (C2MOS)
57. CMOS domino logic
58. Cascaded voltage switch logic
59. Pass transistor logic
60. CMOS technology logic circuit structures
61. Scaling of MOS Circuits
62. Technology Scaling
63. International Technology Roadmap for Semiconductors (ITRS)
64. Scaling Models and Scaling Factors for Device Parameters
65. Implications of Scaling
66. Interconnect Woes
67. Reachable Radius
68. Dynamic and Static Power
69. Productivity and Physical Limits
70. Limitations of Scaling
71. Substrate doping
72. Depletion width
73. Limits of miniaturization
74. Limits of interconnect and contact resistance
75. Limits due to subthreshold currents
76. Limits due to subthreshold currents
77. System
78. VLSI design flow
79. 3 Structured Design Approach
80. Regularity
81. MOSFET as a Switch
82. Parallel and series connection of switches
83. CMOS INVERTER
84. NAND gate Design
85. NOR gate Design
86. CMOS Properties
87. Complex gates
88. Complex gates AOI

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